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Description: The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice.
Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive.
The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.-The LatticeMico8™ is an 8-bit microcontroller optimized for Field Programmable Gate Arrays (FPGAs) and Crossover Programmable Logic Device architectures from Lattice.
Combining a full 18-bit wide instruction set with 16 or 32 General Purpose registers, the LatticeMico8 is a flexible Verilog and VHDL reference design suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive.
The core consumes minimal device resources, less than 200 Look Up Tables (LUTs) in the smallest configuration, while maintaining a broad feature set.
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Size: 1155072 |
Author: 郭豪偉 |
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Description: Verilog 2001 编程规范中文版，作为ASIC和FPGA逻辑开发人员学习不可多得的资料，也可以作为逻辑开发高手们学习查阅的工具。新手们可以按照实例自己编程操练。
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Size: 2236416 |
Author: 徐杰猛 |
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Description: 11路串行AD采集芯片TLC2543，12BIT精度输出，100Khz，采用VERILOG HDL编写，占用200个LE-11-Channel Serial AD acquisition chip TLC2543, 12BIT accuracy of the output, 100Khz, using VERILOG HDL preparation, taking up 200 LE
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Size: 32768 |
Author: chenwl |
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Description: 200分频的verilog综合仿真源程序，以及仿真波形-200divition-200 points frequency integrated simulation verilog source code, and the simulation waveform-200divition
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Size: 94208 |
Author: wangy |
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Description: verilog控制VGA显示器显示一幅像素为200*200的图片。-verilog control VGA display a 200 x 200 pixel images.
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Size: 3655680 |
Author: 李鸣 |
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Description: TinyCPU源码,使用Verilog编写的资源占用极少的CPU。Quartus工程，可跑在Altera MAXII CPLD上,也很方便移植到其他FPGA上。CPU使用200个逻辑单元，外设(SPI,LCD等)使用180个逻辑单元。
内含汇编编译器源码(VC2008)，可编译CPU对应的汇编文件。-The sourcecode of TinyCPU, which only consumed very few logical cells, written by Verilog. It is a Quartus project, and it can run well on Altera MAXII CPLD, and it is conveniently change to other FPGAs. The CPU used 200 Logical Cells, and the device (peripherals such as SPI, LCD) used 180 Logical Cells.
It also included a assembler source code (by VC2008), which can compile the asm file for the CPU.
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Size: 60416 |
Author: 肖海云 |
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Description: 以Actel FPGA作为控制核心，通过自然采样法比较1个三角载波和3个相位差为1 200的正弦波，利用Verilog HDL语言实现死区时间可调的SPWM全数字算法，并在Fushion StartKit开发板上实现SPWM全数字算法。(With Actel FPGA as the control core, between 1 and 3 triangular carrier phase difference of 1200 sine wave by natural sampling, realize the adjustable dead time using Verilog HDL language of the SPWM digital algorithm and digital SPWM algorithm is realized in Fushion StartKit development board.)
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Size: 148480 |
Author: 所罗门
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Description: Verilog实现的DVB（200,168）的RS编解码程序，xilinx 平台，经过验证(Verilog implementation of DVB (200168) RS codec program, Xilinx platform, verified)
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Size: 2214912 |
Author: maplecetc22
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Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
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Size: 10222592 |
Author: 丶大娱乐家 |
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